This application claims priority to Korean Patent Application 2002-0001246, filed on Jan. 9, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor memory devices, and more particularly, to sense amplifier driver circuits for semiconductor memory devices.
A typical semiconductor memory device has a plurality of bit cells, such as memory cells, and a plurality of sense amplifiers for sensing and amplifying data through bit lines which are connected to the bit cells in a read operation. The sense amplifiers are driven by a sense amplifier driver circuit that receives external clock signals and generates a sense amplifier-driving signal.
FIG. 1 illustrates a portion of a static random access memory (SRAM), and FIG. 2 illustrates waveforms for a read operation of the SRAM. Referring to FIG. 1, an SRAM bit cell 11 includes NMOS pass transistors N13 and N14 and a latch 111 having PMOS transistors P11 and P12 and NMOS transistors N11 and N12. Referring to FIG. 2, when a word line WL is activated into a logic high state, the NMOS pass transistors N13 and N14 are turned on so as to develop data, which is stored in the latch 111 of the bit cell, through bit lines BL and BLB. A sense amplifier 13 senses and amplifies the data through the bit lines BL and BLB in response to a sense amplifier-driving signal SAEN, which is generated by a sense amplifier driver circuit 15.
In order to stably perform the sensing operation of the sense amplifier 13, the sense amplifier driving signal SAEN is typically activated after sufficiently developing the data stored in the latch 111 of the bit cell through the bit lines BL and BLB. A period from the activation of the word line WL to the development of the data stored in the latch 111 to a predetermined valid level on the bit lines BL and BLB, is referred to as Tbit. A period from the activation of the word line WL, i.e., the activation of an internal clock signal ICK input to the sense amplifier driver circuit 15, to the activation of the sense amplifier driver circuit 15 is referred to as Td. It is preferable that the period Td is the same as or slightly longer than the period Tbit. The internal clock signal ICK is generated from an external clock signal.
When the period Td is shorter than the period Tbit, an unstable sensing operation of the sense amplifier 13 may occur. When the period Td is excessively longer than the period Tbit, the speed of the sensing operation may be lowered. Consequently, it is preferable that the period Td is slightly longer than the period Tbit, and it is more preferable that the period Td is the same as the period Tbit. Accordingly, in designing an SRAM semiconductor device, it is desirable that the period Tbit be precisely estimated, and the sense amplifier driver circuit 15 designed to generate the period Td such that it is the same as or slightly longer than the period Tbit.
The period Tbit may be affected by various factors, especially by an RC delay due to a parasitic capacitance and parasitic resistance of the bit lines BL and BLB, and by the characteristics of the pass transistors N13 and N14 that drive the bit lines BL and BLB. The parasitic capacitance and parasitic resistance of the bit lines BL and BLB, and the characteristics of the pass transistors N13 and N14 typically vary according to manufacturing process, operating voltage, and temperature. Consequently, the period Tbit typically varies according to the manufacturing process, the operating voltage, and the temperature.
FIG. 3 is a circuit diagram illustrating the sense amplifier driver circuit shown in FIG. 1. The sense amplifier driver circuit 15 includes a plurality of delay inverters 31, 33, 35, and 37 that are connected in series. In FIG. 3, although four delay inverters are shown, the sense amplifier driver circuit 15 may include an even number of delay inverters other than four. The delay inverters 31, 33, 35, and 37 delay and invert an internal clock signal ICK.
The internal clock signal ICK is input through the input of the first delay inverter 31, and the sense amplifier driving signal SAEN, formed by delaying the internal clock signal ICK for the period Td (the sum of delay periods of the delay inverters), is output from the output of the last delay inverter 37. The internal clock signal ICK is generated from an external clock signal.
FIG. 4 illustrates a conventional implementation of the delay inverters shown in FIG. 3, and FIG. 5 illustrates another conventional implementation of the delay inverters shown in FIG. 3. The conventional circuit in FIG. 4 includes a PMOS transistor P41, an NMOS transistor N41, an RC delay element formed by capacitances C41 and C42 and resistances R41 and R42, and a fuse F41 for varying a delay period. The conventional delay inverter shown in FIG. 5 includes a PMOS transistor P51 and an NMOS transistor N51 having a small beta ratio xcex2, where the beta ratio xcex2 is a ratio of width to length.
A frequent problem with the delay inverters shown in FIGS. 4 and 5 is that the change in the period Td may or may not track the change in the period Tbit, depending on the manufacturing process, the operating voltage, and the temperature. When the manufacturing process, the operating voltage, and the temperature vary, the variation of the period Tbit may be larger than the variation of the period Td, so that the period Td may become shorter than, or excessively longer than, the period Tbit. Consequently, the sensing operation of the sense amplifier 13 may be unstable or the speed of the sensing operation may undesirably decrease.
FIG. 6 is a graph of simulation results showing the periods Td and Tbit in an SRAM having a conventional sense amplifier driver circuit as shown in FIG. 4. FIG. 7 is a table illustrating various working conditions corresponding to various combinations of manufacturing process, operating voltage, and temperature used for the simulation of FIG. 6. In FIG. 7, HIGH operating voltage refers to 1.35 V, LOW operating voltage refers to 1.05 V, LOW temperature refers to xe2x88x9255xc2x0 C., HIGH temperature refers to 125xc2x0 C., FAST process refers to a fast process parameter for a 0.13 um CMOS process, and SLOW process refers to a slow process parameter for a 0.13 um CMOS process.
Referring to FIG. 6, the periods Td and Tbit are significantly different except for the working condition 11. In particular, the period Td is excessively longer than the period Tbit for the working condition 16, in which the performance of the SRAM is the worst of the illustrated cases. In this case, the sensing speed of the sense amplifier 13 undesirably decreases, which can degrade the performance of the SRAM.
In an SRAM having a conventional sense amplifier driver circuit, the RC delay elements of the bit lines BL and BLB shown in FIG. 1 and of the delay inverters shown in FIG. 4 and the driving performances of the pass transistors N13 and N14 shown in FIG. 1 and of the delay inverters shown in FIG. 4 generally have different characteristics according to the working conditions. Accordingly, the period Tbit typically does not closely track the change in the period Td in response to variations of process, operating voltage, and temperature.
In some embodiments of the present invention, a sense amplifier driver circuit of an SRAM includes a plurality of delay inverters connected in series, wherein at least one delay inverter includes a plurality of NMOS transistors connected to an output in series while having gates connected to an input, and the overall beta ratio (a ratio of width to an entire length of the NMOS transistors) of the NMOS transistors is the same as the beta ratio of a pass transistor in the bit cell. It is preferable that the length of the NMOS transistors is substantially the same as the length of the pass transistor in the bit cell and that the width of the NMOS transistors is different from the width of the pass transistor in the bit cell.
In further embodiments of the present invention, a sense amplifier driver circuit of SRAM includes a plurality of delay inverters connected in series, wherein at least one delay inverter has a plurality of NMOS transistors connected to an output in series while having gates connected to an input. A plurality of PMOS transistors is connected to the output in parallel while having gates connected to the input. The overall beta ratio of the NMOS transistors is substantially the same as the beta ratio of a pass transistor in the bit cell. It is preferable that the length of the NMOS transistors is substantially the same as the length of the pass transistor in the bit cell and that the width of the NMOS transistors is different from the width of the pass transistor in the bit cell.
According to still further embodiments of the present invention, a sense amplifier driver circuit of SRAM includes a plurality of delay inverters connected in series, wherein at least one delay inverter has a plurality of NMOS transistors connected to an output in series while having gates connected to an input, and a plurality of PMOS transistors connected to the output in series while having gates connected to the input, wherein the overall beta ratio of the NMOS transistors is the same as the beta ratio of a pass transistor in the bit cell. It is preferable that the length of the NMOS transistors is substantially the same as the length of the pass transistor in the bit cell and that the width of the NMOS transistors is different from the width of the pass transistor in the bit cell.
In further embodiments of the invention, a sense amplifier driver circuit for generating a sense amplifier enable signal that enables a sense amplifier that drives a bit line coupled to a pass transistor of a memory cell includes an inverter that generates the sense amplifier enable signal. The inverter includes a pull-down circuit including a plurality of series-connected MOS transistors of the same conductivity type as the pass transistor. The plurality of series-connected MOS transistors may have an overall channel width/length ratio that is substantially the same as a channel width/length ratio of the pass transistor. The aggregate length of the series-connected transistors may be substantially the same as a length of the pass transistor, and widths of the series-connected transistors may be different from a width of the pass transistor.
In some embodiments, the inverter comprises at least one PMOS transistor having a source electrode coupled to a first power supply node, and a series-connected plurality of NMOS transistors coupled between a drain electrode of the at least one PMOS transistor and a second power supply node. Gate electrodes of the at least one PMOS transistor and the NMOS transistors are commonly connected. The inverter may further comprise a fuse connected in parallel with at least one of the series-connected NMOS transistors.
In further embodiments, the inverter comprises a PMOS transistor having a source electrode coupled to a first power supply node, and a series-connected plurality of NMOS transistors coupled between a drain electrode of the PMOS transistor and a second power supply node. Gate electrodes of the PMOS transistor and the NMOS transistors are commonly connected.
In still further embodiments, the inverter comprises a plurality of PMOS transistors having source electrodes coupled in common to a first power supply node and a series-connected plurality of NMOS transistors coupled between commonly connected drain electrodes of the PMOS transistors and a second power supply node. Gate electrodes of the PMOS transistors and the NMOS transistors are commonly connected.
In additional embodiments, the inverter comprises a series-connected plurality of PMOS transistors having a source electrode coupled to a first power supply node, and a series-connected plurality of NMOS transistors coupled between a drain electrode of the series-connected PMOS transistors and a second power supply node. Gate electrodes of the PMOS transistors and the NMOS transistors are commonly connected.